Cyient pushes semiconductor breakeven out by at least a quarter, maybe two
Three months after guiding for an FY27 EBIT-neutral semiconductor business, management now says late FY27 or early FY28 works too.
What's new
- Semiconductor breakeven target moved to late FY27 or early FY28, from FY27 in January.
- Cyient Semiconductors raised ₹300 crore from EAAA Alternatives at a ₹4,650 crore valuation.
- ASSP power semiconductors now account for 50%-60% of semiconductor revenue.
Themes from the call
Breakeven Timeline
The semiconductor business breakeven has been pushed out from FY27 to late FY27 or early FY28, with management signaling further slippage wouldn't bother them.
Capital Structure
₹300 crore raised via ₹200 crore debt and ₹100 crore equity values Cyient Semiconductors at ₹4,650 crore.
Product Mix Shift
ASSP power semiconductors, carrying 50%-60% gross margins, are now the majority of semiconductor revenue.
Guidance watch
- Management now sees breakeven in late FY27 or early FY28, adding that a one-to-two quarter delay would not be a concern.
- Management refused to quantify integration costs or margin impact from the Kinetic Technologies acquisition.
Risk flags
- A flexible, non-committal breakeven timeline makes it harder to model the path to profitability.
- The ASIC pipeline is valued at ~$100 million but conversion depends on multi-quarter customer qualification cycles with no named clients.
- The Kinetic integration plan was not detailed, leaving margin bridge unquantified.
Key quotes
-
"...becoming EBIT neutral in FY27."
— Cyient management, Jan 2026 call -
"...we are still looking at a break-even in late FY27 or early FY28, but based on the investor conversations, we will come back."
— Krishna Bodanapu, CEO, May 2026 call
The brief
Cyient's semiconductor breakeven target has slipped. In January, CEO Krishna Bodanapu guided for an EBIT-neutral semiconductor business in FY27. This quarter he revised that to late FY27 or early FY28, then added that a one-to-two quarter delay would not be a concern. The relaxed framing is a marked shift from the firmer commitment made three months ago. "We will come back" is not guidance. It's a placeholder.
The business itself is taking shape around a clearer three-segment model. ASSP power semiconductors, carrying 50%-60% gross margins, now account for 50%-60% of revenue. That's the strategic priority. The custom ASIC pipeline sits at around $100 million, but conversion depends on multi-quarter qualification cycles and management won't name customers.
To fund the push, Cyient raised ₹300 crore from EAAA Alternatives at a ₹4,650 crore valuation for its semiconductor arm. The capital supports the integration of the acquired Kinetic Technologies platform and scaling of proprietary products. Management detailed the fundraise but did not quantify integration costs.
The core tension is between the long-term thesis and the near-term execution timeline. Management is building power semiconductors for AI data centers and tapping government-backed chip programs. But the breakeven timeline is now open-ended. For a business still in its early revenue stage, that's a lot of weight on a roadmap that keeps shifting. One quarter down. Maybe two. Hard to tell, because management isn't counting.
Cyient's semiconductor arm is gaining shape, but its profitability timeline keeps moving.